A field effect transistor cell comprises the areas of source, drain and body including a channel region. In symmetrical field effect transistors, the cell size is defined by the distance from the axis of symmetry of the body region to the axis of symmetry of the drain region. Small cell sizes are especially important in output stages to achieve a small on-resistance. The cell size is reduced if source and body are provided with a common contact, but this excludes the application of different voltages to source and body, which may be required in some designs of integrated circuits.
U.S. Pat. No. 8,963,243 discloses a p-channel LDMOS transistor with a semiconductor substrate provided with a well of n-type conductivity. A p-type source region, a p+-type source contact region and an n-type body contact region are arranged in the well. The contact regions are separated by an isolation region and provided with separate contacts.
US 2015/0123206 A1 discloses a field effect transistor provided with a body-contact. A gate strip is disposed on a first portion of the active region of a substrate. Source and drain regions are disposed on second and third portions of the active region adjacent to opposite sides of the gate strip. A body-contact region is disposed on a fourth portion of the active region separated from the gate strip by a fifth portion of the active region. The fifth portion of the active region is not covered by any silicide features.